Job Responsibility:
Position entails working with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focusing on physical design of deep sub-micron GPU chips in the areas of floorplanning and timing closure of block level and full chip floor. The individual is expected to have a strong knowledge in multiple aspects of PD areas and to be accountable on project delivery.
Job Requirements:
• Min 5 to 20 years of industrial experience in ASIC design
• Hands on experienced in EDA tools like Encounter / Innovus and ICC2
• Hands on experienced in STA and technique for timing closure
• Understanding of floorplan and layout techniques for foundry rule compliant
• Experience in scripting with TCL, Perl or Python
• Good writing, reading and listening skills in English
• Good communication skills with strong interpersonal skills with flexibility
• Dedicated, hardworking and good team player
• Min 3+ years of projects tapeout experience