Semiconductor
Performance-optimized, comprehensive, and cost-effective solutions with shorter time to market. Building skill based ODCs and expanding project teams with qualified individuals.
Silicon Engineering
Specifications
Architectural Design
Functional & Logic Design
Circuit Design
Physical Design
Fabrication
Packaging & Testing
Chip
RTL Design
Performance-optimized, comprehensive, and cost-effective solutions with shorter time to market. Building skill based ODCs and expanding project teams with qualified individuals.
Microarchitecture Design
Implementation of RTL
Design Verification
Having served numerous tier-1 clients, our design verification team has expertise in simulators,
debugging tools, formal verifiers, and hardware accelerators from all the major EDA tool suppliers.
Utilizing not only OVM/UVM but also the other popular methodologies.
SoC/IP Functional Verification
Low Power Verification, Analog Mixed Signal Verification
Hardware & Software Co-verification
Verification IP Development and Verification
System C /TLM Modelling
Formal Verification
Our verification team understands which tools and methods to apply at the appropriate time based
upon the types of designs and application areas with previous experience across multiple industry
verticals spanning Consumer Electronics, Wireless, Data Centre, Automotive, and Memory/Storage
segments.
DFT
A excellent Design For Test (DFT) service may not only shorten time-to-market but also significantly
increase execution quality. Our DFT team makes certain of it. We provide the following services to our
clients with quickly developing well-trained staff both in-house and at the customer's location
Physical Design
Our Physical Design teams use their proven flows and processes to build the entire Back End flow
and take full responsibility from RTL/Netlist to GDSII.
Floor Planning
Place & Route
Clock Tree Synthesis
Timing Closure
Signal Integrity
Extract/DRC /LVS
Tape-out
GDSII Generation
With a combined experience of more than 100 years and expertise in each foundry, we assure the
highest possible efficiency, power, and area (PPA).
Analog Layout
Since its inception, we can deliver high-quality Analog IC layout for different applications in
semiconductor design with the following expertise:
Double patterning techniques
DSM sub 7nm &10nm complex DRCs
Variable metal grids
Density checks
Reliability verification checks
Electromigration checks
Rapid ESD
Latch-up issues
Building customized ESD ADTs
Building customized MIMCAP ADTs
Post layout extraction debugging skills
Special routing for high-speed critical nets
With many reputed clients in the portfolio and an experienced team of motivated experts and
enthusiasts, we are happy to serve you.
Analog Design
With customers ranging from starting in Analog design to some of the largest semiconductor
companies, our team can handle as much as little design work
We will execute your analog circuit design based on your requirements to develop circuit blocks or
subsystems integrated into a larger customer-designed chip.
PLL Designs
DLL Designs
Phase Interpolators
LDO Designs
Bandgap voltage references
Transceiver Designs
Equalizers ( CTLE, DFE, FFE )
Clock Data Recovery (CDR) Calibration blocks.
Sense amplifier latches
Resistor compensation circuits
ADC and DAC AFEs
Termination Circuits
ESD Implementation
Channel modeling and Wire modelling
Silicon Engineering
- Specifications
- Architectural Design
- Functional & Logic Design
- Circuit Design
- Physical Design
- Fabrication
- Packaging & Testing
- Chip Packaging and Testing
RTL Design
- Design Expertise:
- Comprehensive SoC Capabilities:
- End-to-End Support:
Our team excels in ASIC design, covering Architectur, Micro-Architecture, IP Development, Soc integration, Flow bringup and signoff including Compilation, Linting, CDC, RDC, Fistail, Synthesis, LEC, VCLP, Power Artist, PTPX and more.
Boasting proficiencies in ARM processors, RISC-V, and FPGAs like Altera, Xilinx, and Microsemi, Modernize specializes in IP design for various protocols, including PCIE, Ethernet, USB, UNIPRO, MIPI-CSI, MIPI-DSI, and 802.11ac/11x.
From conceptualizing to production, Modernize provides Architecture development, IP Design, SOC Configuration, Integration, Constraint development, validation, and signoff, with a dedicated team addressing design challenges and ensuring cost-effective development.
Design Verification
- SoC/ASIC/Subsystems/IP Functional Verification-I2C,USB,DDR,Ethernet & PcI
- Verification planning, feature extraction, capturing functional coverage and check points
- Architecting Testbench & developing reusable verification environment
- Metric & coverage driven verification
- Processor/ARM Based SoC Verification
- Creation of reference models using traditional HDL languages and advanced HVL languages like System Verilog, C, C++ and System C
- Automation and Regression management
- Gate level simulation (GLS)
- End-to-end verification closure from specification to RTL signoff
- Low-power verification– power estimation, CPF/UPF
- Analog Mixed Signal Verification
- Verification IP Development and Verification
- Pre-Silicon and Post-Silicon Validation/Verification
DFT
- DFT Architecture, Implementation and validation
- Scan design architecture, Scan insertion and compression
- ATPG Pattern Generation for various fault models (Stuck-at, Transition, Bridging and Cell aware Fault Model) and Fault Coverage Analysis.
- MBIST Implementation & Memory Testing
- High test coverage with fault models, BIST for memory and logic
Physical Design
- Floor Planning
- Place & Route
- Clock Tree Synthesis
- Timing Closure
- Signal Integrity
- Extract/DRC /LVS
- Tape-out
- GDSII Generation
- Foundries : TSMC, Samsung, Intel, GF & UMC
- Technology Nodes :3nm,5nm, 7nm, 10nm, 14nm, 16nm & above
- Tools: Cadence & Synopsys flow
Analog Layout
- Analog layout: Opamps, Bandgap, Bias, ADC, DAC and temp sensors
- Power management layout : Buck & Boost, LDO and power amplifiers
- Clocking layouts : PLL, DLL, Oscillators, VCO and CDRs
- Rf Layouts : LNA, Mixers, Filters and RADAR
- High speed IO layouts : GPIO, LVDS, DDR, LPDDR and SERDES.
- Memory layouts: Single port, multi port and SRAM.
- ESD layouts : HBM, MM and CDMD
- TSMC, Global Foundry, UMC, IBM, SAMSUNG, Tower Jazz and Micron.
- Technology Nodes : 16nm,14nm,10nm,7nm,5nm and 3nm.
- DRC, LVS, ERC, PERC, DFM, EM & IR, Antenna
Analog Design
- Timing and Clock Generations
- Power Management (LDO, Buck-Boost Regulators)
- RF Power Amplifiers
- IO (Input/Output) Circuit
- SERDES (Serializer/Deserializer)
- Analog and data converters
- High presion bangap generators , ADC DAC convertors.
- Clock Data Recovery (CDR) Calibration blocks.
Silicon Engineering
- Specifications
- Architectural Design
- Functional & Logic Design
- Circuit Design
- Physical Design
- Fabrication
- Packaging & Testing
- Chip Packaging and Testing
RTL Design
- Design Expertise:
-
- Comprehensive SoC Capabilities:
-
- End-to-End Support:
Design Verification
- SoC/ASIC/Subsystems/IP Functional Verification-I2C,USB,DDR,Ethernet & PcI
- Verification planning, feature extraction, capturing functional coverage and check points
- Architecting Testbench & developing reusable verification environment
- Metric & coverage driven verification
- Processor/ARM Based SoC Verification
- Creation of reference models using traditional HDL languages and advanced HVL languages like System Verilog, C, C++ and System C
- Automation and Regression management
- Gate level simulation (GLS)
- End-to-end verification closure from specification to RTL signoff
- Low-power verification– power estimation, CPF/UPF
- Analog Mixed Signal Verification
- Verification IP Development and Verification
- Pre-Silicon and Post-Silicon Validation/Verification
DFT
- DFT Architecture, Implementation and validation
- Scan design architecture, Scan insertion and compression
- ATPG Pattern Generation for various fault models (Stuck-at, Transition, Bridging and Cell aware Fault Model) and Fault Coverage Analysis.
- MBIST Implementation & Memory Testing
- High test coverage with fault models, BIST for memory and logic
Physical Design
- Floor Planning
- Place & Route
- Clock Tree Synthesis
- Timing Closure
- Signal Integrity
- Extract/DRC /LVS
- Tape-out
- GDSII Generation
- Foundries : TSMC, Samsung, Intel, GF & UMC
- Technology Nodes :3nm,5nm, 7nm, 10nm, 14nm, 16nm & above
- Tools: Cadence & Synopsys flow
Analog Layout
- Analog layout: Opamps, Bandgap, Bias, ADC, DAC and temp sensors
- Power management layout : Buck & Boost, LDO and power amplifiers
- Clocking layouts : PLL, DLL, Oscillators, VCO and CDRs
- Rf Layouts : LNA, Mixers, Filters and RADAR
- High speed IO layouts : GPIO, LVDS, DDR, LPDDR and SERDES.
- Memory layouts: Single port, multi port and SRAM.
- ESD layouts : HBM, MM and CDMD
- TSMC, Global Foundry, UMC, IBM, SAMSUNG, Tower Jazz and Micron.
- Technology Nodes : 16nm,14nm,10nm,7nm,5nm and 3nm.
- DRC, LVS, ERC, PERC, DFM, EM & IR, Antenna
Analog Design
- Timing and Clock Generations
- Power Management (LDO, Buck-Boost Regulators)
- RF Power Amplifiers
- IO (Input/Output) Circuit
- SERDES (Serializer/Deserializer)
- Analog and data converters
- High presion bangap generators , ADC DAC convertors.
- Clock Data Recovery (CDR) Calibration blocks.